m255
K4
z2
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z0 dC:/questasim64_10.6c/examples
T_opt
!s110 1589298390
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04 8 4 work delay_tb arch 1
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o-quiet -auto_acc_if_foreign -work work
tCvgOpt 0
n@_opt
OL;O;10.6c;65
R0
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Z3 DPx4 ieee 14 std_logic_1164 0 22 eNV`TJ_GofJTzYa?f<@Oe1
Z4 dD:/project_vhdlcode/delay
Z5 8D:\project_vhdlcode\delay\delay.vhd
Z6 FD:\project_vhdlcode\delay\delay.vhd
l0
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!s100 LEhf1Z4_fTA[k3ZG7^YK93
Z7 OL;C;10.6c;65
32
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!i10b 1
Z9 !s108 1589298466.000000
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Z11 !s107 D:\project_vhdlcode\delay\delay.vhd|
!i113 0
Z12 o-work work -2002 -explicit
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Abehavioral
R2
R3
DEx4 work 5 delay 0 22 9UJJ=9Q:HCM5URD>DU3Wa2
l15
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!s100 2CaC>EczUB<UA3KakCGB02
R7
32
R8
!i10b 1
R9
R10
R11
!i113 0
R12
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Edelay_tb
Z14 w1589298462
Z15 DPx4 ieee 9 math_real 0 22 Sk6CSihbPL<f[^Shm]=KX0
Z16 DPx4 ieee 11 numeric_std 0 22 :ASDNFgHXf_ih3J@9F3Ze1
R2
R3
R4
Z17 8D:\project_vhdlcode\delay\delay_tb.vhd
Z18 FD:\project_vhdlcode\delay\delay_tb.vhd
l0
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!s100 UXPYHN0ohU7^93D1l<ZXH1
R7
32
R8
!i10b 1
R9
Z19 !s90 -reportprogress|300|-work|work|-2002|-explicit|-vopt|-stats=none|D:\project_vhdlcode\delay\delay_tb.vhd|
Z20 !s107 D:\project_vhdlcode\delay\delay_tb.vhd|
!i113 0
R12
R13
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R15
R16
R2
R3
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l21
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Z22 VcXmFiJP`iH7PIZn@L<EUG3
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R7
32
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!i10b 1
R9
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R20
!i113 0
R12
R13
